Research
Interests
One promising avenue for continued performance and efficiency improvements in future microprocessors is to employ single-ISA heterogeneous chip multi-processors (HCMPs). All cores in an HCMP implement the same instruction set, but the core microarchitectures differ. This allows architects to leverage the fact that no single microarchitecture is always best for all program phases. The benefit of an HCMP hinges on the ability to migrate program phases to the core which can most efficiently execute that phase. However, program phases can be very short. We have found that the benefit of HCMPs increases as the interval between allowable migrations is decreased. This necessitates a migration that introduces as little overhead as possible, since overhead can potentially eliminate the benefit gained by migrating to other cores when phases are short.
My research generally revolves around processor architecture and design, including techniques for improving performance and efficiency. More specifically, I am focusing my research on exploring the alternatives for the fast migration of architectural register values in an effort to maximize the benefit of HCMPs.
Publications
Forbes, J. E., Characterization of Load Address Idioms with Implications for Address Prediction. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2008. [link]
Al-Otoom, M., Forbes, E., and Rotenberg, E., "EXACT: Explicit Dynamic-Branch Prediction with Active Updates," Proceedings of the 7th ACM International Conference on Computing Frontiers, pp. 165-176, May 2010. [link]
Dechene, M., Forbes, E., and Rotenberg, E., "Multithreaded Instruction Sharing," Department of Electrical and Computer Engineering, North Carolina State University, Technical Report CESR-TR-2010, December 2010. [pdf]
Rotenberg, E., Dwiel, B. H., Forbes, E., Zhang, Z., Widialaksono, R., Chowdhury, R. B. R., Tshibangu, N., Lipa, S., Davis, R., and Franzon, P. D., "Rationale for a 3D Heterogeneous Multi-core Processor," Proceedings of the 31st IEEE International Conference on Computer Design, pp. 154-168, Oct. 2013. [link]
Franzon, P., Rotenberg, E., Tuck, J., Davis, W. R., Zhou, H., Schabel, J., Zhang, Z., Park, J., Dwiel, B., Forbes, E., Huh, J., Priyadarshi, S., Lipa, S., and Thorolfsson, T., "Applications and design styles for 3DIC," Proceedings of the 2013 IEEE International Electron Devices Meeting, pp. 29.4.1-29.4.4, Dec. 2013. [link]
Forbes, E., Choudhary, N. K., Dwiel, B. H., and Rotenberg, E., "Design Effort Alloy: Boosting a Highly Tuned Primary Core with Untuned Alternate Cores," Proceedings of the 32nd IEEE International Conference on Computer Design, pp. 408-415, Oct. 2014. [link]
Forbes, E., Basu Roy Chowdhury, R., Dwiel, B., Kannepalli, A., Srinivasan, V., Zhang, Z., Widialaksono, R., Belanger, T., Lipa, S., Rotenberg, E., Davis, W. R., Franzon, P. D., "Experiences with Two FabScalar-Based Chips," 6th Workshop on Architectural Research Prototyping, held in conjunction with ISCA-42, June 2015. [pdf]
Forbes, E., Zhang, Z., Widialaksono, R., Lipa, S., Dwiel, B., Rotenberg, E., Davis, W. R., and Franzon, P. D., "Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor," Poster at 27th Hot Chips: A Symposium on High Performance Chips, August 2015. [link]
Franzon, P., Rotenberg, E., Tuck, J., Davis, W. R., Zhou, H., Schabel, J., Zhang, Z., Park, J., Dwiel, B., Forbes, E., Huh, J., Priyadarshi, S., and Lipa, S., "Computing in 3D," IEEE Custom Integrated Circuits Conference, September 2015. [link]
Forbes, J. E., Hardware Thread Migration for 3D Die-stacked Heterogeneous Multi-core Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2016. [link]
Ku, S., Forbes, E., Basu Roy Chowdhury, R., and Rotenberg, E., "Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures," Poster at 53rd Design Automation Conference, June 2016. [pptx]
Forbes, E. and Rotenberg, E., "Fast Register Consolidation and Migration for Heterogeneous Multi-core Processors," Proceedings of the 34th IEEE International Conference on Computer Design, pp. 1-8, Oct. 2016. Winner of best paper award in Processor Architecture track. [link]
Ku, S., Forbes, E., Basu Roy Chowdhury, R., and Rotenberg, E., "A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures," Proceedings of the 18th International Symposium on Quality Electronic Design, pp. 131-137, Mar. 2017. [link]
Srinivasan, V., Basu Roy Chowdhury, R., Forbes, E., Widialaksono, R., Zhang, Z., Schabel, J., Ku, S., Lipa, S., Rotenberg, E., Davis, R., Franzon, P., "H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor," Proceedings of the 35th IEEE International Conference on Computer Design, pp. 145-152, Nov. 2017. [link]
Severeid, J. and Forbes, E., "dt: A High-level Assembler for RISC-V," Proceedings of the 53rd Midwest Instruction and Computing Symposium, April 2020. [pdf]
Severeid, J. and Forbes, E., "Technical Reference for the dt Programming Language and Assembler," Department of Computer Science, University of Wisconsin-La Crosse, Technical Report TR04032020, April 2020. [pdf]
Grunwald, A., Nguyen, P. and Forbes, E., "dptv: A New PipeTrace Viewer for Microarchitectural Analysis," Proceedings of the 55th Midwest Instruction and Computing Symposium, pp. 274-284, March 2023. [pdf]
Other works currently under peer review.