elliott forbes

Curriculum Vitae

J. Elliott Forbes, Ph.D., Computer Engineering

Contact

219 Wing Technology Center
Department of Computer Science
University of Wisconsin-La Crosse
La Crosse, WI 54601
(608) 785-6819

Education

North Carolina State University, Raleigh, NC
Doctor of Philosophy, Computer Engineering, May 2016
Emphasis: Computer architecture
Advisor: Eric Rotenberg

North Carolina State University, Raleigh, NC
Master of Science, Computer Engineering, December 2008

Michigan Technological University, Houghton, MI
Bachelor of Science, Computer Engineering, April 2005

Publications

[1] Forbes, J. E., Characterization of Load Address Idioms with Implications for Address Prediction. M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, December 2008.

[2] Al-Otoom, M., Forbes, E., and Rotenberg, E., "EXACT: Explicit Dynamic-Branch Prediction with Active Updates." Proceedings of the 7th ACM International Conference on Computing Frontiers, pp. 165-176, May 2010.

[3] Dechene, M., Forbes, E., and Rotenberg, E., "Multithreaded Instruction Sharing," Department of Electrical and Computer Engineering, North Carolina State University, Technical Report CESR-TR, December 2010.

[4] Rotenberg, E., Dwiel, B. H., Forbes, E., Zhang, Z., Widialaksono, R., Chowdhury, R. B. R., Tshibangu, N., Lipa, S., Davis, R., and Franzon, P. D., "Rationale for a 3D Heterogeneous Multi-core Processor," Proceedings of the 31st IEEE International Conference on Computer Design, pp. 154-168, Oct. 2013.

[5] Franzon, P., Rotenberg, E., Tuck, J., Davis, W. R., Zhou, H., Schabel, J., Zhang, Z., Park, J., Dwiel, B., Forbes, E., Huh, J., Priyadarshi, S., Lipa, S., and Thorolfsson, T., "Applications and design styles for 3DIC," Proceedings of the 2013 IEEE International Electron Devices Meeting, pp. 29.4.1-29.4.4, Dec. 2013.

[6] Forbes, E., Choudhary, N. K., Dwiel, B. H., and Rotenberg, E., "Design Effort Alloy: Boosting a Highly Tuned Primary Core with Untuned Alternate Cores," Proceedings of the 32nd IEEE International Conference on Computer Design, pp. 408-415, Oct. 2014.

[7] Forbes, E., Basu Roy Chowdhury, R., Dwiel, B., Kannepalli, A., Srinivasan, V., Zhang, Z., Widialaksono, R., Belanger, T., Lipa, S., Rotenberg, E., Davis, W. R., Franzon, P. D., "Experiences with Two FabScalar-Based Chips," 6th Workshop on Architectural Research Prototyping, held in conjunction with ISCA-42, June 2015.

[8] Forbes, E., Zhang, Z., Widialaksono, R., Lipa, S., Dwiel, B., Rotenberg, E., Davis, W. R., and Franzon, P. D., "Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor," Poster at 27th Hot Chips: A Symposium on High Performance Chips, August 2015.

[9] Franzon, P., Rotenberg, E., Tuck, J., Davis, W. R., Zhou, H., Schabel, J., Zhang, Z., Park, J., Dwiel, B., Forbes, E., Huh, J., Priyadarshi, S., and Lipa, S., "Computing in 3D," IEEE Custom Integrated Circuits Conference, September 2015.

[10] Forbes, J. E., Hardware Thread Migration for 3D Die-stacked Heterogeneous Multi-core Processors. Ph.D. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, March 2016.

[11] Ku, S., Forbes, E., Basu Roy Chowdhury, R., and Rotenberg, E., "Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures," Poster at 53rd Design Automation Conference, June 2016.

[12] Forbes, E. and Rotenberg, E., "Fast Register Consolidation and Migration for Heterogeneous Multi-core Processors," Proceedings of the 34th IEEE International Conference on Computer Design, pp. 1-8, Oct. 2016. Winner of best paper award in Processor Architecture track.

[13] Ku, S., Forbes, E. Basu Roy Chowdhury, R., and Rotenberg, E., "A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures," Proceedings of the 18th International Symposium on Quality Electronic Design, pp. 131-137, Mar. 2017.

[14] Srinivasan, V., Basu Roy Chowdhury, R., Forbes, E., Widialaksono, R., Zhang, Z., Schabel, J., Ku, S., Lipa, S., Rotenberg, E., Davis, R., and Franzon, P., "H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor," Proceedings of the 35th IEEE International Conference on Computer Design, pp. 145-152, Nov. 2017.

[15] Siever, B., Chamberlain, R. D., Forbes, E., and Russell, I., "Including Embedded Systems in CS: Why? When? and How?," Proceedings of the ACM Special Interest Group on Computer Science Education, pp. 328-329, Feb. 2019.

[16] Doll, D., Rutherford, D., Kernozek, T., Forbes, E., "Visualizing Real-time Feedback of a Rehabilitation Trainer," Proceedings of the 2019 Midwest Instruction and Computing Symposium, Apr. 2019.

Other works currently under peer review.

Grants

• Multi-frequency Dual Pipetrace Viewer and Performance Debugger, UW-L Faculty Research Grant, July 2017-June 2018

• A Software Tool-set for Undergraduate Computer Architecture Projects, UW-L Teaching Innovation Grant, July 2019-June 2020

Professional Service

• Program committee member, 37th IEEE International Conference on Computer Design, 2019

• Program committee member, 36th IEEE International Conference on Computer Design, 2018

• Program committee member, 33rd IEEE International Parallel & Distributed Processing Symposium, 2019

Academic Experience

Assistant Professor: August 2016-Present
University of Wisconsin-La Crosse

• Developed curriculum and courses, and obtained approval from department, university and system committees, for a new bachelor of science in computer engineering.

• Courses Taught:
CS 120 - Software Design I
CS 220 - Software Design II
CS 272 - Digital Circuit Design for Microcontrollers I
CS 370 - Computer Architecture
CS 372 - Digital Circuit Design for Microcontrollers II
CS 419 - Special Topics (Systems Development)
CS 472 - Internet of Things

Graduate Research Assistant: August 2007-August 2009, May 2012-May 2016
North Carolina State University

• Exploring the design space of solutions to improve the physical design quality of automated synthesis, placement, and routing (see [6][11][13])
• Implemented and explored the advantages of a register file value-swapping mechanism in SystemVerilog to support a fast-thread migration architecture in a 3DIC (see [4][5][7][8][9][10][12][14])
• Researching performance extensions to a simultaneous multithreaded processor (see [3])
• Researching the interaction between address computation and the load instructions which use those addresses (see [1]), the results were used to guide design decisions for an advanced branch predictor (see [2])

Adjunct Instructor: August 2009-December 2009, August 2010-May 2012
North Carolina State University

ECE 109 - Introduction to Computer Systems
• Developing course materials and lecturing a 150+ student introductory course covering many topics in computer engineering, including data representation, basic digital circuits, computer arithmetic and system architecture, and assembly programming
• Implementing new curricula to introduce multi-core concepts to students as part of an NSF-funded Early Adopters program
• Directing teaching assistants for lab and grading duties
• Managing course sections offered as distance education

Graduate Teaching Assistant: August 2006-April 2007
North Carolina State University

• ECE 109 - Introduction to Computer Systems
• ECE 200 - Introduction to Signals, Circuits and Systems
• ECE 209 - Computer Systems Programming

Honors / Awards

• Winner of best paper award in Processor Architecture track at ICCD-34 October 2016
• MIT Lincoln Labs GFP Fellowship Recipient: June 2007-June 2008
• Member of Eta Kappa Nu, Beta Eta Chapter: Inducted October 2006
• Michigan Tech Dean's List: May 2001-May 2005

Student Honors / Awards

• Phuong Nguyen: Winner of Dean's Distinguished Fellowship 2017 -- UW-L College of Science and Health

Industry Experience

Intel Corp., Hillsboro, OR

• Graduate Intern Technical: April 2010-August 2010
• Path-finding for architectural support for dynamic binary translation

Intel Corp., Folsom, CA

• Graduate Intern Technical: June 2007-August 2007
• Graphics driver testing for GM45 chipset

Smiths Aerospace Ltd. Contracted through Technisource Inc., Grand Rapids, MI

• Technical Contractor: June 2005 to June 2006
• Graphics hardware and driver testing for C-130 AMP

Unisys Corp., Roseville, MN

• Student Technical: Various interships January 2002 to August 2004
• ASIC physical design and characterization for ClearPath IX